1. Field of the Invention
This invention relates to the dense packaging of electronic circuitry and to the stacking of semiconductor integrated circuit (IC) chips also referred to as “die” or “integrated circuit die” herein. More specifically, the invention relates to a process for de-packaging warped integrated circuit die in a prepackaged integrated circuit to correct planarity imperfections to provide enhanced uniformity in the final die for use in IC stacking applications.
The invention is an enabling technology for providing a substantially planar integrated circuit die for use in the fabrication of a “neo-layer” and “neo-wafer”.
2. Description of the Related Art
The ability to fabricate very thin, stackable layers containing one or a plurality of homogeneous or heterogeneous integrated circuit chips is desirable and allows high density, high speed electronic systems to be assembled for use in military, space, security and other applications.
Examples of such layers and modules are disclosed in U.S. Pat. No. 6,072,234, entitled Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes, U.S. Pat. No. 6,797,537, Method of Making Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers, U.S. Pat. No. 6,784,547, Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers, U.S. Pat. No. 6,117,704, Stackable Layer Containing Encapsulated Chips, U.S. Pat. No. 6,072,234, Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes, U.S. Pat. No. 5,953,588, Stackable Layers Containing Encapsulated IC Chips, and U.S. Pat. No. 7,768,113, entitled Stackable Tier Structure Comprising Prefabricated High Density Feed-through.
The stacking and interconnection of very thin microelectronic layers permits high circuit speeds in part because of short lead lengths with related reduced parasitic impedance and reduced electron time-of-flight. These desirable features combined with a very high number of circuit and layer interconnections allow relatively large I/O designs to be implemented in a small volume.
The present invention provides a stackable integrated circuit die having an enhanced planarity and uniformity for use in multi-layer, microelectronic modules such as are disclosed in the above referenced patents which permit die having different functions and therefore different areas to be stacked as if they were same size die.
A prior art process for making a “neo-chip” or “neo-layer” involves the “potting” of individual IC chips in a encapsulant or compound which supports and insulates each chip and which can be cut or diced to provide equal area layers so that chips having different sizes can be stacked in layers whose edges are coplanar with one another. The individual chips, in die form, may be incorporated into neo-wafer form for processing. Thereafter, layers are cut out of the neo-wafer and incorporated into stacks.
The prior art neo-layer processes may include the processing and stacking of chips purchased as individual die. Beneficially, chips purchased as individual die are generally “known good” die, which have been “burned in”, and are therefore pre-tested prior to stacking.
Prior to stacking, one or more known good die are used to create the “neo-wafer”, by locating those known good die in a potting fixture. Potting material is flowed into the fixture, which is enclosed and then the potting material is cured. The resulting “neo-wafer” is removed from the fixture and then subjected to pre-stacking process steps, including spinning on a layer of dielectric material, forming vias through that material to reach the terminals on the die in the wafer, and then forming electrical conductors on the surface of the dielectric layer leading from the die terminals. Thereafter the neo-wafer is diced into one or more layers suitable for stacking, each layer containing at least one of the known good die.
Each layer of a completed stack has electrical leads which connect the IC circuitry of the embedded chip or chips to one or more access planes, where the electrical leads are available for connection to exterior circuitry.
Major cost-saving benefits can be obtained by the sole use of “known good” die, and the use of a neo-wafer in processing one or more of such die.
Neo-stacking offers significant improvements over bare silicon die stacking, but it also proved troublesome under certain market circumstances. In particular, it is often difficult to obtain bare die because many manufacturers will only sell packaged die.
For instance, when trying to buy bare DRAM die from a particular manufacturer, it was discovered that the manufacturer would not sell bare DRAM die, but would sell the DRAM die already pre-tested and installed in prepackaged integrated circuit packages.
Because of the demand for die and the high capital investment necessary to be a mass manufacturer of them, it is difficult to induce a mass fabricator of die to supply only die as opposed to the usual finished product which is a packaged or encapsulated integrated circuit chip. Such mass fabricators are typically fully occupied with the manufacture of finished and packaged integrated circuits. Individual IC chips are not typically offered for sale either in wafer or in die form.
Even in those cases where a mass fabricator can be induced to manufacture and sell a bare functional die, the die may only be supplied in wafers or diced without testing. In other words, a die is normally tested after it is connected to its lead frame and packaged to ascertain whether it is operable as intended. Mass testing of bare die is not a procedure that many mass fabricators are equipped or even inclined to do. Therefore, a purchaser of bare die must test each die individually in order to determine its operability or the yield. Bare die testing is too limited to ensure acceptable yields, while comprehensive testing and burn-in renders bare die production cost-ineffective. These problems are sometimes referred to as the known good die or KGD problem.
Because prepackaged parts are burned in and therefore contain known good die, it is sometimes desirable or necessary to depackage the known good die within a prepackaged IC package for use in certain applications such as the above neo-processes.
A present concern in providing KGD from de-packaged IC chips is the observation that certain types of thinner IC chips (less than 250 microns thick) are provided with a non-uniform planarity, i.e., are warped inside the package encapsulant material whereby the active surface area of the IC chip having electronic circuitry defined thereon is concave.
A difficulty arises when depackaging prepackaged integrated circuit die (such as by grinding or lapping away a predetermined portion of encapsulant on the upper and lower surface of the prepackaged part) in that the die within the package may be warped across its surface. In such cases, the lapping or grinding process steps can result in the removal of an operable portion of the chip itself (i.e., the active surface of the integrated circuit die), a feature that is undesirable for use in neo-layers.
The warped die condition is due to IC package fabrication processes with the result being that the upper, active surface of the die in, for instance, a ball grid array package material is slightly concave, i.e., warped, which warped condition is exacerbated as the encapsulating material is progressively removed during depackaging.
Applicant has observed conditions in which the ends of prepackaged die are approximately 35 to 45 microns above the internal package substrate while the center of die is approximately 15 microns above the substrate. Non-planarity or warpage has been measured in some packages with a difference of about 50 microns from the end of the die to its center, which is unacceptable in certain die stacking applications.
Because of the above-described integrated circuit package conditions, processes such as grinding and lapping to depackage (i.e., to remove encapsulant material) the die can worsen the final die thickness uniformity, sometimes resulting in removal of the active IC semiconductor material from the die before the desired final die thickness is achieved.
What is needed is a method whereby known good die can be economically and practically obtained from packaged known good die and that have enhanced planarity and surface uniformity.